1. Field of the Invention
The present invention relates to a high speed electrical signal interconnect structure for transferring data, and in particular, the present invention relates to an optimum interconnect structure among multiple Dynamic Random Access Memory devices in order to accommodate high speed signals.
2. Art Background
It is common to build a computer that includes one or more small circuit boards designed to accommodate surface-mount memory chips. These so called "Single In-line Memory Modules" (SIMMs) were developed to use less board space and are more compact than more conventional memory-mounting hardware. A SIMM may be comprised of one of several different types of random access memory (RAM). RAM is semiconductor-based memory that can be read and written by the microprocessor or other hardware devices. These storage locations can be accessed in any order. While the various types of Read Only Memory (ROM) are capable of random access, the term "RAM", is generally understood to refer to volatile memory, which can be written as well as read. Examples of types of RAM include: Dynamic RAM (DRAM), Static RAM (SRAM) and Video RAM (VRAM).
DRAMs store information in integrated circuits that contain capacitors. Because capacitors lose their charge over time, DRAMs must include logic to "refresh" (recharge) the RAM chips periodically. While a DRAM is being refreshed, it cannot be read by the processor; if the processor must read the RAM while it is being refreshed, one or more wait states occur. Because their internal circuitry is simple, DRAMs are more commonly used than SRAMs, even though they are slower. A DRAM can hold approximately four times as much data per area as a SRAM of the same complexity.
SRAM is based on the logic circuit known as the flip-flop, which retains the information stored as long as there is enough power to run the device. Because SRAMs are more expensive than DRAMS, SRAMs are usually reserved for special fast memory subsystems called caches, in which frequently used data values are stored for quick access.
VRAM is a special type of DRAM used in high-speed video applications. With conventional DRAM, both the processor and the video circuitry must access RAM by sharing the same control pins on the RAM chips. VRAM provides separate pins for the processor and the video circuitry. The processor accesses the VRAM in a manner almost identical to that for DRAM, but the video circuitry is provided with a special "back door" to the VRAM. This back door lets the video circuitry access the memory bit by bit (serially), which is more appropriate for transferring pixels to the screen than is the parallel access provided by conventional DRAM.
As computers have become faster and more powerful, it has become desirable to increase the amount of RAM available on an individual SIMM. However it is not the question of simply increasing the number of RAM chips on a SIMM. Every RAM chip added onto the SIMM increases the load seen by the bus driver of the computer system. A driver is a hardware device that controls or regulates another device. A line driver, for example, boosts signals transmitted over a communications line, and a bus driver amplifies and regulates signals transmitted over a bus (data pathway) thereby providing a strong signal across multiple lines concurrently. Doubling or quadrupling the number of RAM chips on a SIMM will result in a corresponding increase in the SIMM load seen by the bus driver. Such an increase in load would exceed the capability of the bus driver.
While it is common in the art for SIMM boards to have a plurality of DRAM modules on a SIMM, the driver is typically located on a separate board with a significantly long interconnect between the driver on the board and the memory modules located on the SIMM. Most SIMMs only contain memory chips, thereby relying on the bus driver to supply the signals to the memory chips. Some prior art SIMM boards have an on-board driver for each memory module. However, simply adding on-board drivers will not maintain the signal integrity requirements necessary in the case of a high density, high speed memory module.
Signal integrity is important when at high signal speeds as each RAM chip must receive the signals concurrently with each other RAM chip on the SIMM. Synchronizing signals so that each RAM chip receives its signal concurrently with every other RAM chip becomes increasingly difficult as the density of the SIMM increases because there are simply more chips to receive the signal and hence more possibilities for one of the chips to lose synch. This increased opportunity for synchronization problems is further compounded by the closer tolerances demanded by the high speed signals. At high speeds, signals change more rapidly, more possible transitions in a given time interval occur, and each possible transition provides a chance for loss of synchronization. Moreover, each signal transition must be accomplished in a shorter time providing each RAM chip a very small amount of time to correctly respond to the signal.
For the high operating speeds of the present state of the art, using multiple on-board drivers will not provide an adequate high speed interconnect necessary to take advantage of the more sophisticated access times. The close tolerances of high speed signals would require that the multiple drivers operate in a virtually identical manner to guarantee that each RAM chip receives its signal concurrently with every other RAM chip. Yet each driving chip manufactured varies slightly in its operating characteristics from other driving chips of the same type. For the reasons outlined above, the tolerable margin of error when selecting matching driving chips decreases as the operating speed of the SIMM increases. This matching problem is further compounded as the number of drivers placed on the SIMM board increases because each additional driver must match every driver already selected.
Just as the bus driver may not be powerful enough to drive the large number of chips on a high density SIMM, a single on-board driver also may not have the power to drive such a large number of chips. Moreover, even if a driving chip of sufficient strength is used, increasing the number, and hence, the density of the RAM chips on the SIMM board necessarily increases the length of the signal paths used to connect the chips together. If no on-board driver, or only a single on-board driver, is used, each RAM chip must be connected to a single signal source. The physical size of each individual RAM chip forces the chips to be disbursed across the SIMM board in such a way that longer lead lengths cannot be avoided. Increased lead lengths cause reflection signal noise which can cause glitches (non-monotonic wave forms). Non-monotonic waveforms appear as multiple rising edges, where only one rising edge was desired. These glitches can result in the wrong data being stored in, or retrieved from, the memory thereby destroying the reliability of the computer's computations.
Referring now to FIG. 1, a typical high speed digital signal is demonstrated. The square wave 1 represents an ideal signal. Voltage on the line may be in either of two states (low or high). These states may be thought of as corresponding to two arbitrary opposite states which have been chosen for their suitability based upon the particular function of the signal. Representative naming conventions include: on/off, zero(0)/one(1), Read/Write. The speed of the signal is judged by the number of possible times per second that the signal can transition from one state to another. Thus for a typical high speed signal with a frequency of 40 Megahertz, the signal would have a maximum of 40 million high/low states per second. Each state would last 25 nanoseconds (billionths of a second).
Superimposed upon the square wave is a more representative "clean" (low-noise) signal 2. It is impossible for the signal to transition instantaneously from the low to high states (or back to low again) as is represented in the step function of the square wave. In reality, there is a rise and fall time, that results in the sloping leading edge 3 and trailing edge 4 demonstrated here. In the present art, for a 40 Megahertz system, this rise/fall time is approximately 2 nanoseconds.
Referring now to FIG. 2, one finds a simplified representative noisy signal 6. When the wave hits an impedance discontinuity, i.e. a branch in the printed circuit board trace, the voltage of the wave is split between the branches producing a step. The waveforms flowing down the branches do not reach the maximum voltage, Vo, until the reflections from the branches return. (A good analogy is an ocean wave flowing up two creeks). The voltage before the discontinuity, Vo, will divide into two voltages Vo/X1 in the first branch and Vo/X2 in the second branch (where X1 and X2 are both greater than one). If the reflections do not return within the risetime of the signal, the Vo/X1 or the Vo/X2 voltage is observable and thus a glitch is formed.
The time that it takes for the signal to reflect back is a function of the speed of light, the length of travel of the signal along its path and the dielectric constant of the board. For a fixed dielectric constant, the relationship is such that the longer the length of the signal path, the longer the delay to the inflection point.
If the signal has several terminal points, then there will be as many inflection points as there are different length paths to the terminal points and combination of inflection points may produce false triggers. For present art, low density, slow speed SIMMs, the connection distances are short enough so that false triggers do not occur. This is because the wave returns during the risetime period of the signal.